1. Field of the Invention
The present invention relates to a structure of a non-volatile memory device and a method for fabricating the same. More particularly, the present invention relates to a structure of a flash memory device method and a method for fabricating thereof.
2. Description of Related Art
A flash memory device provides the property of multiple entries, retrievals and erasures of data. Moreover, the stored information is retained even electrical power is interrupted. As a result, the non-volatile memory device is widely used in personal computers and electronic systems.
A typical flash memory device employs doped polysilicon for the formation of the floating gate and the control gate. During the programming and the erasing of this type of flash memory device, an appropriate voltage is applied to the source region, the drain region and the control gate to inject electrons into and to eject electrons from the polysilicon floating gate.
In general, electron injection for a flash memory device includes the channel hot-electron injection (CHEI) model and the Fowler-Nordheim Tunneling model. The programming and the erasing of a device are accomplished by either the injection or ejection of electrons.
Referring to FIG. 1, FIG. 1 is a schematic diagram, illustrating the structure of a conventional stacked gate flash memory (U.S. Pat. No. 6,214,668). A conventional flash memory device is formed with a p-type substrate 100, a deep N-type well region 102, a P-type well region 104, a stacked gate structure 106, a source region 108, a drain region 110, a spacer 112, an inter-layer dielectric layer 114, a contact 116 and a conductive line 118. The stacked gate structure 106 comprises a tunnel oxide layer 120 a floating gate 122, a gate dielectric layer 124, a control gate 126 and a gate cap layer 128. The deep N-type well 102 is located in the P-type substrate 100. The stacked gate structure 106 is disposed on the substrate 100. The source region 108 and the drain region 110 are located beside the aides of the stacked gate structure 106 in the P-type substrate 100. The spacer 112 is disposed on the sidewall of the stacked gate structure 106. The P-type well region 104 is located in the N-type deep well region 102, extending from the drain region 110 to substrate 100 underneath the stacked gate structure 106. The interlayer dielectric layer 114 is disposed on the P-type substrate 100. The contact 116 penetrates through the inter-layer dielectric layer 114 and the substrate 100, short-circuiting the P-type well region 104 and the drain region 110. The conductive line 118 is disposed above the interlayer dielectric layer 114 and electrically connected with the contact 116.
During the fabrication of the flash memory device illustrated in FIG. 1, the P-type well region 104 formed by forming a music layer (not shown) on the entire P-type substrate 100 subsequent to the formation of the stacked gate structure 106. This mask layer exposes a predetermined region for forming the drain region. A tilt angle (0 degrees to 180 degrees) ion implantation process is then conducted to implant dopants to the deep N-type well region 102 in the P-type substrate 100 near the drain region on one side of the stacked gate structure 100, using the stacked gate structure 106 and the mask layer as a mask. A drive-in process is then performed to extend the P-type well region 104 to the substrate 100 under the stacked gate structure 106.
During the formation of the stacked gate structure, the silicon oxide etching rate is normally increased to completely remove the grid-shaped gate dielectric layer in order to prevent the gate dielectric layer debris remaining on the sidewall of the floating gate. The field oxide layer, not covered by the floating gate layer, is then over-etched to form a trench. Consequently, dopants that are implanted during the tilt angle ion implantation process (30 to 50 electronic volts of implantation energy) for the formation of the P-type well region 104 would penetrate through the field oxide layer, inducing a current leakage of the memory cell at the side of the drain region. Further, an ineffective isolation between the bit lines is resulted.
Additionally, to form the local P-well region, the subsequent dopant drive-in process is conducted under a temperature of 900 degrees Celsius and an oxygen gas ambient. The tunnel oxide layer along the edge of the floating gate 122 and the gate dielectric layer 124 (silicon oxide/silicon nitride/silicon oxide) would become thicker. Further, the diffusion of the P-well driving-in is difficult to control. The efficiency and the yield of the device are adversely affected.
Further, the source regions of the flash memory devices is connected together through the deep N-type well region to form a source line. Since the resistance of a deep N-type well region is higher, the operational speed is affected. In order to increase the operational speed, a source line pickup is conventionally formed at every 16 memory cells in the active region, in other words, 16 bit lines, to lower the resistance of the deep N-type well region (source line). However, forming a source line pickup in the active region would lower the ration of the memory cell array. The integration of the device thereby can not be increased.
Further, during the formation of the contact 116, the interlayer dielectric layer 114 and the P-type substrate 100 are etched to form a contact that penetrates through the interlayer dielectric layer 114 and the drain region 110. The aspect ratio of the contact is thus very high. Moreover, two different materials (silicon oxide and silicon) are etched. Controlling the depth of the contact is thus very difficult. The difficulty of the manufacturing process is thereby increased. Also, during the back-end processing, the contact of the memory cell region and the contact of the periphery circuit region need to be separated. The back-end processing thus becomes more complicated.